Modern integrated circuits include a very large amount of clock signal sequence circuit s such as flip flops, logic gates and the like. The design process is relatively long and includes multiple stages such as high level description, synthesis, placement and routing, extraction, static timing analysis and the like.
In order to test modern integrated circuits various Design For Testability (DFT) techniques were developed. Various DFT techniques include the following stages: (i) loading test patterns into the integrated circuit, including scan chains formed within the integrated circuit, (ii) launching a test sequence by providing one or usually multiple launch clock signals, (iii) capturing test results by providing one or more capture clock signals, and (iv) shifting out the test results.
The following U.S. patents, U.S. patent applications and articles provide a brief review on some state of the art DFT methods and devices: U.S. Pat. No. 6,728,917 of Abramovici et al., titled “Sequential test pattern generation using combinational techniques”; U.S. Pat. No. 5,513,123 of Dey et al., titled “Non-scan design-for-testability of RT-level data paths”; U.S. Pat. No. 6,598,192 of McLaurin et al. (hereinafter—“McLaurin”); U.S. patent application publication number 2004/0177299 of Wang et al., titled “Scalable scan-path test point insertion technique”; U.S. patent application publication number 2005/0066242 of Wang et al., titled “Hybrid scan-based delay testing technique for compact and high fault coverage test set”; U.S. patent application publication number 2003/0188245 of Abramovici et al., titled “Sequential test pattern generation using clock-control design for testability structures”; U.S. patent application publication number 2004/0237015 of Abdel-Hafez et al., titled “Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits”; U.S. patent application publication number 2003/0188239 of Hosokawa et al., titled “Compacted test plan generation for integrated circuit testing, test sequence generation, and test”; U.S. patent application publication number 2002/0024352 of Sim, titled “Semiconductor integrated circuit with test points inserted thereto”; U.S. patent application publication number 2003/0084390 of Tamarapalli et al., titled “At-speed test using on-chip controller” (hereinafter—“Tamarapalli”); and “The testability features of the ARM1026EJ microprocessor core”, T. L. McLaurin, F. Frederick, R. Slobodnik, ITC International Test Conference, 2003.
Various tests should be executed at the functional speed of the chip. These tests are also referred to as at-speed tests. The execution of these tests is relatively costly and complex, for various reasons. First, an external test device (also refereed to as Automated Test Equipment ATE) that is required to generate functional speed signals is relatively costly. Second, even if such a device exists then the pins (or associated interface circuitry) of the integrated circuit can distort the high speed signals. In many cases the core of the integrated circuit operates at a high frequency and the pins are not adapted to manage signals of such a high frequency.
Tamarapalli suggests to solve at-speed testing problems by switching between low frequency external signals that can be provided during the scanning stage of the test, and between internally generated high frequency signals. These high frequency signals are generated by an PLL circuit and are provided via a complex clock synchronizer and switching mechanism to a tested core.
McLaurin suggests to manipulate an PLL clock signal by chopping the signal such as to provide clock sequences that can include two adjacent clock signals that are very close to each other. The chopping mechanism can be controlled by a set of registers, each storing a predefined chopping sequence.
There is a need to provide an efficient system and method for high speed testing of integrated circuits.